1. Field of the Invention
The present invention relates to a logical circuit for detecting an electric potential, with a high speed, at a potential detecting point relatively large in load, on the basis of a clock signal and an input signal.
2. Description of the Prior Art
FIG. 1 of the attached drawings is a view showing an arrangement of a CMOS logical circuit of dynamic type, while FIG. 2 is a view showing operational timing of the logical circuit illustrated in FIG. 1.
As shown in FIG. 1, the logical circuit is controlled in conductivity by a clock signal .phi., and comprises a MOS transistor (hereinafter referred to as "PMOS") 101 of the P-channel type which pre-charges a potential detecting point to high-order power-source potential (series connecting point) N1, a logical switch 102 connected in series to the PMOS 101 through the series connecting point N1 for short-circuiting the connecting point N1 and a ground power-source potential V.sub.SS on the basis of a plurality of inputs I.sub.1 -I.sub.n and an inverter circuit 103 for detecting a change or variation in potential at the connecting point N1. In this connection, a capacitance 104 connected to the connecting point N1 indicates a parasitic capacitance added to the connecting point N1.
Accordingly, as shown in FIG. 2, the logical circuit is arranged such that the series connecting point N1 between the PMOS 101 and the logical switch 102 is pre-charged to the high-order power-source potential V.sub.DD by the PMOS 101 under that conductive condition within a pre-charge period of time, the logical switch 102 subsequently short-circuits the ground point N1 and the ground power-source potential V.sub.SS to each other on the basis of inputs I.sub.1 -I.sub.n during an evaluation period of time, to bring the connecting point N1 to the ground potential, and this change in potential is detected by the inverter circuit 103 and is outputted.
With the arrangement of the logical circuit, the following disadvantage occurs. That is, in the case where the load capacitance 104 at the connecting point N1 is large, the logical switch 102 alters the potential at the connecting point N1 so that, as shown in FIG. 2, the time T.sub.EV until the potential at the connecting point N1 descends from the power-source potential V.sub.DD to a potential V.sub.S at the switching point of the inverter circuit 103 is increased. Thus, detection of the potential change at the connecting point N1 is delayed.
In view of the above, there is a method in which, in order to dissolve the above-discussed deficiency, a circuit constant of FET forming the inverter circuit 103, for example, threshold voltage is altered or changed whereby the potential V.sub.S at a witching point moves toward the power-source potential. Generally, however, it is difficult to largely move the switching point of the inverter circuit. Further, although detection of a change in potential from a high level to a low level is quickened by moving the switching point V.sub.S at the switching point toward V.sub.DD, detection from the low level to the high level is slowed down a great deal. Thus, the method has such a disadvantage that a balance of the detection is deteriorated.
On the other hand, as another method for avoiding of the above-discussed deficiency, as shown in FIG. 3, there is a method in which a transistor pre-charging the connecting point N1 is formed by an NMOS 105, and a pre-charge level at the connecting point N1 is brought to V.sub.DD -V.sub.TN (V.sub.TN is threshold voltage of the NMOS 105). However this method has the following problem. That is, the pre-charge level the connecting point N1 is liable to fluctuate so that an operating margin is reduced. Furthermore, the case where the connecting point N1 is not discharged for a long period of time, the potential at the connecting point N1 is raised to the power-source potential V.sub.DD by leak current in the NMOS 105 at non-conducting. Thus, the potential cannot be detected with a high speed.
As described above, the conventional logical circuit of the dynamic type, which detects a change in potential, causes the following deficiency. That is, high-speed detection of the potential is difficult in the case where the load capacitance at the potential detecting point is large, and if an attempt is made to execute the potential detection with high speed, the balance of detection is deteriorated, and the operational margin is reduced.